4_in_1 結構

module top;
system_clk #200 clk1(a);
system_clk #100 clk2(b);
system_clk #50 clk3(c);
system_clk #25 clk4(d);
a4_in_1 n1(f,a,b,c,d);
endmodule

module a4_in_1(f,a,b,c,d);
input a,b,c,d;
output f;
wire c1,d1,x,y;
not(c1,c);
not(d1,d);
and(x,c1,d1);
and(y,c,d1);
or(f,x,y);
endmodule

module system_clk(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(PERIOD-1)$stop;
endmodule