1228 期末考 4_in_1

module top;
system_clk #200 clk1(a);
system_clk #100 clk1(b);
system_clk #50 clk1(c);
system_clk #25 clk1(d);
a4_in_1 n1(f,a,b,c,d);
endmodule

module a4_in_1(f,a,b,c,d);
input a,b,c,d;
output f;
wire f1,f2,f3,f4,f5;
wire a1,b1,c1,d1;
not(a1,a);
not(b1,b);
not(c1,c);
not(d1,d);
and(f1,c,d);
and(f2,a1,b1,c);
and(f3,a1,b,d);
and(f4,a,b,c);
and(f5,a,b1,c1,d1);
or(f,f1,f2,f3,f4,f5);
endmodule

module system_clk(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
#(PERIOD-1)$stop;
endmodule